1. Technical Field
Various embodiments relate to a semiconductor apparatus and, more particularly, to a circuit and a method for generating an on-die termination (ODT) signal of a semiconductor apparatus.
2. Related Art
In general, a semiconductor apparatus, and particularly a memory apparatus, performs an impedance matching operation in order to communicate data with a system. In other words, the impedance matching between the memory apparatus and the system is performed so that the data can be smoothly communicated therebetween. Such an impedance matching between the semiconductor apparatus and the system is referred to as an on-die termination (ODT).
FIG. 1 is a block diagram schematically showing a configuration of a conventional ODT signal generating circuit. As shown in FIG. 1, the ODT signal generating circuit includes an ODT pad 11, an ODT buffer 12, a clock pad 21, a clock buffer 22, an additive latency (AL) unit 30, and a column address strobe (CAS) write latency (CWL) unit 40. An external ODT signal ODT_ext is inputted through the ODT pad 11 and the ODT buffer 12, and an external clock signal CLK is inputted through the clock pad 21 and the clock buffer 22. The additive latency unit 30 receives the buffered external ODT signal ODT_ext and the buffered external clock signal CLK, and delays the external ODT signal ODT_ext based on additive latency information. The CAS write latency unit 40 receives the clock signal CLK and an output ODT_AL of the additive latency unit 30, and delays the output ODT_AL of the additive latency unit 30 based on CAS write latency information CWL<5:8> to generate an ODT control signal ODT_int.
FIG. 2 is a diagram showing a configuration of the CAS write latency unit 40 of FIG. 1. As shown in FIG. 2, the CAS write latency unit 40 includes an AND gate 41, first to third multiplexers (MUX) 42, 43 and 44, and first to sixth flip-flops FF1 to FF6 which are coupled in series with one another. The AND gate 41 receives the output ODT_AL of the additive latency unit 30 and the CAS write latency information CWL<8>. The first to third multiplexers 42, 43 and 44 are configured to receive the CAS write latency information CWL<7>, CWL<6> and CWL<5>, respectively, and output either the output ODT_AL of the additive latency unit 30 or the output of the respective one of the first to third flip-flops FF1, FF2 and FF3, which are coupled to the first to third multiplexers 42, 43 and 44, respectively. The first to sixth flip-flops FF1 to FF6 are configured to sequentially delay the output ODT_AL of the additive latency unit 30 in response to the clock signal CLK. The CAS write latency unit 40 delays the output ODT_AL of the additive latency unit 30 by as much as “CWL-2” to output the delayed signal as the ODT control signal ODT_int.
For example, if CWL is 7, the first multiplexer 42 outputs the output ODT_AL of the additive latency unit 30 to the second flip-flop FF2 in response to the CAS write latency information CWL<7>. The output ODT_AL of the additive latency unit 30 can then be delayed by the second to sixth flip-flops FF2 to FF6 by as much as 5 periods of the clock CLK and finally be provided as the ODT control signal ODT_int.
FIGS. 3 and 4 are timing diagrams illustrating exemplary operations of the conventional ODT signal generating circuit. In a memory apparatus, the additive latency (AL) can be determined in relation to a CAS latency (CL), such as, for example, AL=0, AL=CL−1 or AL=CL−2. For purposes of illustrating an exemplary operation, it is assumed that AL=0, CW=7, and burst length (BL)=8.
In FIG. 3, when a write command WT is applied from the system, the external ODT signal ODT_ext is applied at the same time. Since AL=0, the additive latency unit 30 outputs the ODT signal ODT_ext without any delay. Since CWL=7, the CAS write latency unit 40 delays the output ODT_AL of the additive latency unit 30 by as much as 5 periods of the clock CLK to generate the ODT control signal ODT_int. Afterwards, the ODT control signal ODT_int is inputted to an ODT driver (not shown) to be a signal instructing impedance determination and a source signal used for generating a data strobe signal DQS. Accordingly, the data strobe signal DQS is generated in response to the ODT control signal ODT_int. As shown in FIG. 3, when the ODT control signal ODT_int is generated, a preamble of the data strobe signal DQS corresponding to a single clock period is generated and, thereafter, a strobe pulse is generated so that BL=8.
The data strobe signal DQS indicates a timing point at which data is inputted/outputted to smoothly input/output the data. Thus, the data strobe signal DQS prepares for the data input/output operation by generating a preamble before the data is substantially inputted/outputted. Recently, with the increasing operation speed of semiconductor apparatuses, a data transmission speed has also increased. Therefore, it may be difficult to ensure an accurate data input/output operation with only the conventional preamble corresponding to a single clock period. Therefore, there exists a need for generating a preamble corresponding to 2 clock periods so that the semiconductor apparatus can be more stably prepared for the data input/output operation.
FIG. 4 is a timing diagram showing an operation of a conventional ODT signal generating circuit that generates the preamble of the data strobe signal corresponding to 2 clock periods. As shown in FIG. 4, the external ODT signal ODT_ext should be inputted before the write command WT is inputted in order to generate the preamble of the data strobe signal DQS corresponding to 2 clock periods. Requiring the external ODT signal ODT_ext to be inputted before the write command WT may result in a time loss because the write command WT must either be inputted after being delayed in the system or be delayed after being inputted from the system. In addition, it may decrease the channel efficiency between the system and the semiconductor apparatus.